Apple, IBM and Motorola formed the AIM alliance to develop a mass market version of the POWER processor…

1.1.         The 801 research project

In 1974 IBM started a project to build a telephone switching computer, this machine would need only to perform I/O, branches, add register-register, move data between registers and memory, and would have no need for special instructions to perform heavy arithmetic. This simple design philosophy, whereby each step of a complex operation is specified explicitly by one machine instruction, and all instructions are required to complete in the same constant time, would later come to be known as RISC. When the telephone switch project was cancelled IBM kept the design for the general purpose processor and named it 801. As a result of eliminating seldom used instructions, the IBM 801 had slightly less than a hundred commands, while Intel’s 8086 had over 400.

1.2.         The America project

In 1985, and after Cheetah Project in 1982, research on a second-generation RISC architecture started producing the “AMERICA architecture”; in 1986, IBM started developing the RS/6000 series computers based on that architecture. This was to become the first POWER architecture.

1.3.         POWER I, II

The original POWER microprocessor, one of the first superscalar RISC implementations, was a high performance, multi-chip design. IBM soon realized that a single-chip microprocessor was needed in order to scale its RS/6000 line from lower-end to high-end machines. Work on a one-chip POWER microprocessor, designated the RSC (RISC Single Chip) began.

In early 1991, IBM realized its design could potentially become a high-volume microprocessor used across the industry.

While in 1993, continued improvements in the POWER1 processor architecture led to the POWER2 processor.

POWER Architecture features:

  • Fixed-length instructions, with three operands format.
  • Register-to-Register architecture,
  • Simple addressing modes,
  • Large general register file
  • Three-operand instruction format.
  • Superscalar
  • Branching technique

1.4.         PowerPC

In 1992, IBM approached Apple with the goal of collaborating on the development of a family of single-chip microprocessors based on the POWER architecture. Soon after, Apple, being one of Motorola’s largest customers of desktop-class microprocessors, asked Motorola to join the discussions due to their long relationship, its more extensive experience with manufacturing high-volume microprocessors than IBM, and to form a second source for the microprocessors. Apple, IBM and Motorola formed the AIM alliance to develop a mass market version of the POWER processor. In 1993, and with the result of this alliance was the “PowerPC architecture”, a modified version of the POWER architecture.

2.    PowerPC and RISC Architecture

The RISC (Reduced Instruction Set Computer) architecture evolved in the 1970s. In a RISC machine, the instruction set contains simple instructions with limited addressing modes—a “reduced” instruction set. Compilers can emit a sequence of simple RISC instructions to take the place of a corresponding set of complex CISC instruction.

In addition to the reduced instruction set, RISC processors often employ:

  • Register operations to minimize memory accesses
    • Integrated caches to minimize slower RAM memory accesses
    • A pipeline model to process one or more instructions per clock cycle

3.    PowerPC’s Special Features

PowerPC is a standard RISC design that adds a few unique features of its own, including:

  • A Branch Processor to keep the fixed-point and floating-point units busy despite the presence of branches in the instruction stream
  • Multiple specialized processors: a Branch Unit, Floating-Point Unit, and Fixed-Point Unit, each with its own instruction set and ability to operate independently
  • Support for misaligned storage accesses
  • Support for “big-endian” and “little-endian” byte orderings

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